MARVIN Family of Camera Processor IP cores

The MARVIN family of camera processor IP cores is a complete video and still picture image processing unit which is targeted for SoCs with image capture capability generally used in mobile phones with integrated cameras.  The MARVIN products are offered in five versions with resolutions of 2, 3, 5, 8 and 12 megapixels. MARVIN cores contain image processing, scaling and compression functions. The integrated image processing functions allow simple CMOS sensors, without any image preprocessing, to be supported as well as sensors with integrated YCbCr processing.

Applications: Digital Still Cameras & Camcorders , Mobile Phones/Cameras , Portable Multimedia Players

Other Features & Benefits

• 12-bit camera interface (RGB Bayer input)
• MIPI & SMIA serial input interface
• Maximum input resolution of 12 Megapixels
• Bad pixel detection and correction
• Lens shade correction (vignetting)
• Video image stabilization support
• Auto focus measurement
• Auto white balancing
• Auto exposure support by brightness measurement
• Histogram calculation
• Flash light control
• Mechanical shutter support
• Black level compensation
• Enhanced color interpolation (RGB Bayer demosaicing)
• Sharpening / blurring / noise filter
• Color correction matrix (cross talk matrix)
• Digital image effects (emboss, sketch, sepia, grayscale, color selection, negative image)
• Super impose, digital zoom & continuous resize support
• ITU-R BT.601 & 656 compliant video interface
• HW JPEG encoder including JFIF1.02 stream generator with programmable quantization and Huffman tables
• Display-ready RGB output in self-picture path
• Rotation in 90° steps for display-ready RGB output
• Max. 105 MHz system & max. 100 MHz sensor clock
• YCbCr 4:2:2 and 4:2:0 processing
• Frame skip support for video encoding (e.g. MPEG-4)
• Format conversion between YCbCr 4:2:2, 4:2:0, 4:1:1 and 4:1:0 formats
• Planar and semi-planar storage format for YCbCr
• 32-bit AHB master interface to system memory supporting four and eight beat bursts
• Power management by software-controlled clock disabling for currently not needed submodules