- Host Protocol
- Optimized for transaction-oriented designs; minimal host overhead
- Supports two command-issuance mechanisms:
- Efficient in both embedded and PC implementations
- Reduces dependency on bridge behavior
- Supports up to 4Mb external Flash for BIOS expansion
- Supports connection to a SATA II-compliant Storage Enclosure Processor (SEP) via on-chip I2C interface
- Supports external Flash or serial EEPROM for programmable subsystem vendor ID/subsystem product ID
- JTAG boundary scan
A reference design for this product is available. Download the Reference Design Brief for more information.